Specification

RTL coding, lint checks

RTL integration

Connectivity checks

Functional Verification

Synthesis & STA

Gate level simulations

Power aware simulations

Placement and Routing

DFT

Custom layout

Post silicon validation

Transistors in hardware design

Semiconductors

PN Junction dioda

BJT

Field Effect Transistor : FET

NMOS

CMOS

FinFET

Combinational logic

Sequential logic

Overview

Env Setup

Special Variables

Data Types

Variables

Operators

Decisions

Loops

Arrays, Strings, Lists, Dictionary

History and Redoing of commands

String Pattern Matching commands

Basics of Synthesis

High Level Synthesis Flow

Reading of Verilog RTL File

Target and Link Libraries

Resolving References with Link Libraries

Reading hierarchical Designs

Reading ddc design

Analyse & Elaborate Commands

Constraining and Compiling RTL

Post Synthesis Output Data

High Level Multi-Voltage Design Concepts

Supplies and Power Domains

Power Ports and Nets

Level Shifters

Power States and PS Table

IC Compiler II Library Manager

ICC Compiler II NDM Cell Library

Cell Library Characteristics

Library Manager Flow

Tech Only NDM Library

Technology-Only Library Flow

Technology File

Read TLU+ Files

Tech Library Preparation

Top Level, Sub-System Level and Block Level Design Setup

Set up initial Design Implementation

Loading Netlist from Synthesis

Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files

Flow Setup and Design Setup

Loop-back to Synthesis for Correlation issues correction

Initial Floorplanning settings

Define Pad Instances (Physical Cells)

Pad Instance co-ordinates

Start Floorplaning

Core Die Size setting

Floorplanning of Pad Instances

Pad Filler Insertion

Define Pad Ring Power Grid

Macro Instance constraints

Macro Instance Array creation

Macro Instance Orientation

Anchor based and Relative Placement of Macro Instances

Macro Instance-Channel settings

Macro Instance placement – Manual

Congestion probability around Macro Instances

Defining Placement Blockages

Running placement

Defining placement strategies

In Place Optimization

Hierarchical Placement

Relative Placement

Congestion analysis and reduction

Macro placement changes to reduce congestion

Standard Cell Placement Constraints

Halo creation for instances

Congestion Analysis with Standard Cell placement

Local Congestion Reduction

Density Screen and Placement Blockage for Standard Cells

Congestion Aware Placement

Re-Check Macro Placement for better Congestion relief

Create Balanced Buffer Trees for High Fanout Net

Defining Power Structure

Logical Power/Ground Connections

Setting Power Network Constraints

Create and Analyze Power Structure

Change Power Constraints and Re-Create to meet IR requirements

Power Ground Pin connection and create Power Rails

Power Network Checks for IR and Resistance

Placement Blockage for Power Network

Incremental Placement

Re-Order Scan connectivity within Chain

Re-Partition Scan connectivity across Chains

SCANDEF file based Scan Chain Re-Ordering

Congestion checks for Overflow again

RC extraction for Net Parasitics

Check Timing for Max Analysis

Run Timing/Congestion aware Placement

Logic Re-Structuring for Placement and Timing

Check Pre-CTS timing based on Global Routing and Detailed Placement

Setting Clock Constraints such as Target Skew, Target Insertion Delay

Clock Root Attributes as Stop, Float and Exclude Pins

Building for Generated and Gated Clocks

Don’t Touch attribute on existing Clock Tree structure

Defining Clock Buffers and Inverters

Set Clock Tree Timing DRCs

Non-Default Clock Routing rules setting

Perform Clock Tree Synthesis and Clock Tree Optimization

Reduce Hold Violations in Data paths and Scan Paths

Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners

Synchronous Clock Balancing

Cross-Clock Delay Balancing

Logical Hierarchy aware CTS

Max and Min Analysis and subsequent Optimization

Fixing Violations

CTS Optimization across other modes and PVT corners (MMMC)

Skew and Insertion Delay checks

Checking Crosstalk on Clock Network

Pre-Route check points

Routing fundamentals

Global Route

Detail Routing

Track Assignment and Route

Refining Detailed Route

Over the Macro routing

Non-Preferred Routing direction

Clock Net Routing

Initial Data path routing

Redundant VIA insertion setting

Post Detailed Route Optimization

Fixing DRC Violations

Post Detailed Route Delay Calculation Algorithms

Crosstalk Delay and Noise Analysis and Fix

Check Leakage Power Dissipation

VT Cell swap for power and timing trade-off

Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD

Reduce Dynamic power

Meet Total Power target

Functional ECO

Timing ECO

Metal Only ECO using Spare Cells for base frozen designs

Antenna Rules and Fixes

Critical Area Analysis

Wire Spreading and widening

Setting minimum metal jog length

Filler Cell Insertion

Metal Fill

Timing Checks after Metal Fill

Parasitic Extraction for SignOff timing analysis

Export Netlist

Export GDSII